A conventional LDMOS device has been in widespread use as an IC device for power control that can be mounted jointly with other semiconductor devices on a chip by forming diffused layers in the lateral direction thereof. FIG. 4 shows a basic structure of a conventional n-channel LDMOS by way of example.
The conventional n-channel LDMOS comprises a p-type silicon substrate 1, an N well layer 2 serving as a drain layer of the LDMOS, a P well layer 3 serving as a substrate of an N-channel MOS, a LOCOS oxide film 4 of a large thickness for the purpose of isolation and mitigation of a drain-to-gate electric field, a gate oxide film 5, a gate electrode (polysilicon film) 6, an N + diffused layer 7 for forming a source and drain, a P + diffused layer 8 for taking out a potential of the P well layer, an insulating layer (for example, a PSD layer by CVD) 9 for insulation of a wiring layer from a transistor region, a metal interconnect layer 10, and a passivation layer 11 for protection of a device.
The device is operated as follows. A desired voltage is applied to the gate electrode 6, whereupon a current channel layer is induced in a surface region of the P well layer 3 as the substrate, directly underneath the gate, thereby causing a current between a drain and a source to flow from the N well layer 2 as a drain region to a source region.
However, advances have recently been made in downsizing and lower power consumption of electronic equipment accompanied by rapid progress in miniaturization of semiconductor devices employed by the electronic equipment. In particular, pronounced miniaturization has since been made in common logic MOSLSIs constituting a system LSI. Meanwhile, there have been made continued efforts for research and development on downsizing of power devices for controlling relatively large power, such as, for example, a high voltage resistant device (HV-CMOS), and LDMOS.
Particularly, in the case of the LDMOS, downsizing thereof is essential in order to mount it jointly with other devices (CMOS logic circuit, bipolar circuit, and so forth) on one chip. Paten Documents 1 , 2, i.e. JP-A 1994-97450 and JP-A 1995-74352, each show a structure for obtaining a high voltage resistant LDMOS transistor while shortening cell pitches by providing a trench in a gate region or between a gate and drain.
Further, in Paten Document 3, namely, JP-A 1997-139438, there is described a structure wherein a parasitic bipolar transistor is formed together with a substrate so as to form a current path when a reverse voltage is applied to a drain, thereby preventing destruction of a device. Still further, in Paten Document 4, namely, JP-A 1998-294463, there is described a structure of a vertical type device with a current path formed in the vertical direction thereof for preventing an electric field from being concentrated in a square part at the bottom of a gate trench, thereby preventing leak current.
With a semiconductor device for power control, however, a structure with a large area is still required in effecting power control, which has been the main stumbling block for implementing downsizing of LSI chips. Accordingly, with the conventional LDMOS structure, there has been a limitation to downsizing of a power control system.